462 Words2 Pages

III SYNTHESIS AND SIMULATIONS RESULTS
The simulation and synthesis work is finally done by the xilinix and modelsim respectively. Figure 5:synthesis results of Fault FFT.
The figures intimate the fault injected FFT,which is checked by the manual error injected via all diferent possibilities by using RTL scripting. Eventhough the soft error is added in the FFT the error detector code 100% detect the errors and corrector correct the errors. Figure 6:synthezised diagram of DMC with Sum of square algm The above synthezised diagram is sucessfully completed by using Xilinix Syntheziser. Sum of Squares (SOSs) check that can be used to detect errors,SOS check is based on the Parseval theorem that states that the SOSs of the inputs to the FFT are equal to the SOSs of the outputs of the FFT except for a scaling factor.DMC is used for multiple bit error Detection and corrections but number of redundancy bit*…show more content…*

In CRC, a sequence of redundant bits, called cyclic redundancy check bits, are appended to the end of data unit so that the resulting data unit becomes exactly divisible by a second, predetermined binary number. Error correction code (ECC) techniques have been widely used to correct transient errors and improve the reliability of memories.here we were tried for FFT. Figure 7:synthesis diagram of SOS based ECC for FFT. The figure 7 is desinged by using verilog language with xilinix synthesis tool.for this design we had to use 4 to 8 bit Fault FFT with ECC Concept.The ECC codes utilize the less area than previous module. Figure 8: simulations result of Effieint ECC for parallel FFT The figure 8 shows the simulations result of the SOS based ECC for parallel FFT,which is checked by the random test bench code in xilinix tool.here we have to reduce almost best case redundancy minimizations.the wave form is indicate the flag register for intimate the Error if happened.in the soft error

In CRC, a sequence of redundant bits, called cyclic redundancy check bits, are appended to the end of data unit so that the resulting data unit becomes exactly divisible by a second, predetermined binary number. Error correction code (ECC) techniques have been widely used to correct transient errors and improve the reliability of memories.here we were tried for FFT. Figure 7:synthesis diagram of SOS based ECC for FFT. The figure 7 is desinged by using verilog language with xilinix synthesis tool.for this design we had to use 4 to 8 bit Fault FFT with ECC Concept.The ECC codes utilize the less area than previous module. Figure 8: simulations result of Effieint ECC for parallel FFT The figure 8 shows the simulations result of the SOS based ECC for parallel FFT,which is checked by the random test bench code in xilinix tool.here we have to reduce almost best case redundancy minimizations.the wave form is indicate the flag register for intimate the Error if happened.in the soft error

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